The low resistivity phase (C-54) of titanium silicide makes titanium silicide particularly attractive for contact and interconnect metallization. However, as the level of integration increases (in other words, as device size shrinks) the use of titanium silicide becomes increasingly challenging. It is difficult to achieve low resistive contacts at the bottom of high-aspect-ratio narrow holes with titanium silicide due to agglomeration and incomplete phase transformation from the high resistivity phase (C-49) to the low resistivity phase (C-54). The phase transformation is utilized because typical deposition methods form the high resistivity C-49 phase, and so post-deposition annealing is generally included during formation of titanium silicide structures to convert the high resistivity C-49 phase to the low resistivity C-54 phase.
Physical vapor deposition (PVD) techniques, such as evaporation and sputtering, are well known processes for depositing titanium films, and additionally chemical vapor deposition (CVD) is also a widely-used technique for forming titanium films in the semiconductor industry. However, conventional techniques for forming titanium films have several shortcomings when utilized for forming titanium silicide in very high-aspect-ratio openings (such as, for example, openings having an aspect ratio of 20 or greater). Such shortcomings can include difficulties in forming the low resistivity C-54 phase, even with a post-deposition anneal; excessive silicon consumption; and agglomeration. Accordingly, it is desirable to develop new methodologies for forming titanium silicide in semiconductor applications.